1. Field of the Invention
The present invention relates generally to MOSFET fabrication, and more specifically, to MOSFET fabrication that uses spacers as masks.
2. Description of Related Art
Trench type power semiconductor devices such as power MOSFETs are well known. Referring to FIG. 1, a typical power MOSFET 10 includes a plurality of trenches 12 formed in semiconductor body 14. Semiconductor body 14 is usually a silicon die that includes an epitaxially grown silicon layer (epitaxial silicon layer) 16 of one conductivity (e.g. N-type) formed over a silicon substrate 18 of the same conductivity, but of higher concentration of impurities. A channel region 20 (sometimes referred to as body region) is formed in epitaxial silicon layer 16 and extends from the top surface of the semiconductor body to a first depth. Channel region 20 has a conductivity opposite to that of epitaxial layer 16 (e.g. P-type). Formed within channel region 20 are source regions 22, which have the same conductivity (e.g. N-type) as epitaxial silicon layer 16.
As is well known, trenches 12 extend to a depth below the depth of channel region 20 and include gate insulation 24, which may be formed with silicon dioxide, on at least the sidewalls of trenches 12. The bottom of each trench 12 is also insulated with silicon dioxide or the like and a gate electrode 26 is disposed within each trench 12. Gate electrodes 26 are typically composed of conductive polysilicon. As is illustrated in FIG. 1, gate electrodes 26 are recessed to a position below the top of the trenches and thereby below the top surface of the semiconductor body. However, gate electrodes 26 may also be “proud” electrodes, or in other words, extend out of trenches 12 and above the top surface of the semiconductor body.
A typical trench type power MOSFET further includes a source electrode 28, which is electrically connected to source regions 22, and a high conductivity contact region 30, which is also formed in channel region 20. High conductivity contact region 30 is highly doped with dopants of the same conductivity as channel region 20 (e.g. P-type) in order to reduce the contact resistance between source contact 28 and channel region 20. A typical trench type power MOSFET 10 further includes a drain electrode 32 in electrical contact with silicon substrate 18.
In operation, a voltage is applied to gate electrodes 26. When this voltage reaches a threshold value (VTH) a channel is formed adjacent each trench 12 in channel region 20, which formed channel has the same conductivity as that of source regions 22 and the region below channel 20 in epitaxial silicon layer 16. As a result, a current may flow between source electrode 28 and drain electrode 32 of the power MOSFET.
As is well known, the density of the current that a power MOSFET may accommodate is directly proportional to the number of formed channels per unit area. Thus, the greater the number of trenches per unit area the more current a device can handle. Because of this relationship, it is desirable to pack as many trenches as possible for a given die area. This can be accomplished by either reducing the distance between trenches and/or reducing the width of each trench. However, traditional fabrication processes can limit the amount of reduction in these dimensions. For example, traditional masking methods used during the fabrication of a power MOSFET make it difficult to reduce trench width. Similarly, traditional masking methods can lead to mask misalignments. To compensate for these potential misalignments, designers may increase the size of the various regions (e.g., the source regions and high conductivity contact regions) of the MOSFET. However, increased sizes lead to larger distances between trenches.